Alliance Memory SDRAM 64 MB Surface, 54-Pin 16 bit TSOP
- RS 제품 번호:
- 230-8429
- Distrelec 제품 번호:
- 304-31-279
- 제조사 부품 번호:
- AS4C4M16SA-6TIN
- 제조업체:
- Alliance Memory
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대량 구매 할인 기용 가능
Subtotal (1 tray of 108 units)*
₩460,291.68
현재 액세스할 수 없는 재고 정보 - 나중에 다시 확인해 주세요.
수량 | 한팩당 | Per Tray* |
|---|---|---|
| 108 - 216 | ₩4,261.96 | ₩460,231.52 |
| 324 - 432 | ₩4,134.12 | ₩446,404.12 |
| 540 - 972 | ₩4,051.40 | ₩437,491.04 |
| 1080 + | ₩3,970.56 | ₩428,760.32 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 230-8429
- Distrelec 제품 번호:
- 304-31-279
- 제조사 부품 번호:
- AS4C4M16SA-6TIN
- 제조업체:
- Alliance Memory
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모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Alliance Memory | |
| Memory Size | 64MB | |
| Product Type | SDRAM | |
| Data Bus Width | 16bit | |
| Address Bus Width | 13bit | |
| Maximum Clock Frequency | 166MHz | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 5.4ns | |
| Number of Words | 1M | |
| Mount Type | Surface | |
| Package Type | TSOP | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 54 | |
| Maximum Operating Temperature | 85°C | |
| Height | 1.2mm | |
| Standards/Approvals | No | |
| Series | AS4C4M16SA-C&I | |
| Length | 22.35mm | |
| Automotive Standard | No | |
| Maximum Supply Voltage | 3.6V | |
| Minimum Supply Voltage | 3V | |
| 모두 선택 | ||
|---|---|---|
브랜드 Alliance Memory | ||
Memory Size 64MB | ||
Product Type SDRAM | ||
Data Bus Width 16bit | ||
Address Bus Width 13bit | ||
Maximum Clock Frequency 166MHz | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 5.4ns | ||
Number of Words 1M | ||
Mount Type Surface | ||
Package Type TSOP | ||
Minimum Operating Temperature -40°C | ||
Pin Count 54 | ||
Maximum Operating Temperature 85°C | ||
Height 1.2mm | ||
Standards/Approvals No | ||
Series AS4C4M16SA-C&I | ||
Length 22.35mm | ||
Automotive Standard No | ||
Maximum Supply Voltage 3.6V | ||
Minimum Supply Voltage 3V | ||
The Alliance Memory 64Mb SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured as 4 Banks of 1M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a Bank Activate command which is then followed by a Read or Write command.
Fast access time from clock: 4.5/5.4/5.4 ns
Fast clock rate: 200/166/143 MHz
Fully synchronous operation
Internal pipelined architecture
1M word x 16-bit x 4-bank
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