Winbond W9751G6NB25I SDRAM 512 MB Surface, 84-Pin 16 bit VFBGA
- RS 제품 번호:
- 242-0781
- 제조사 부품 번호:
- W9751G6NB25I
- 제조업체:
- Winbond
본 이미지는 참조용이오니 재확인이 필요하시면 문의해주세요.
대량 구매 할인 기용 가능
Subtotal (1 pack of 2 units)*
₩10,753.60
마지막 RS 재고
- 최종적인 56 개 unit(s)이 배송 준비 됨
수량 | 한팩당 | 한팩당* |
|---|---|---|
| 2 - 8 | ₩5,376.80 | ₩10,753.60 |
| 10 - 18 | ₩5,273.40 | ₩10,546.80 |
| 20 - 48 | ₩5,160.60 | ₩10,321.20 |
| 50 + | ₩5,066.60 | ₩10,133.20 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 242-0781
- 제조사 부품 번호:
- W9751G6NB25I
- 제조업체:
- Winbond
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Winbond | |
| Product Type | SDRAM | |
| Memory Size | 512MB | |
| Organisation | 32M x 16 | |
| Data Bus Width | 16bit | |
| Address Bus Width | 15bit | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 0.4ns | |
| Number of Words | 32M | |
| Mount Type | Surface | |
| Package Type | VFBGA | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 84 | |
| Maximum Operating Temperature | 95°C | |
| Height | 0.6mm | |
| Standards/Approvals | RoHS | |
| Length | 12.5mm | |
| Series | W9751G6NB | |
| Width | 8 mm | |
| Minimum Supply Voltage | 1.7V | |
| Automotive Standard | No | |
| Maximum Supply Voltage | 1.9V | |
| 모두 선택 | ||
|---|---|---|
브랜드 Winbond | ||
Product Type SDRAM | ||
Memory Size 512MB | ||
Organisation 32M x 16 | ||
Data Bus Width 16bit | ||
Address Bus Width 15bit | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 0.4ns | ||
Number of Words 32M | ||
Mount Type Surface | ||
Package Type VFBGA | ||
Minimum Operating Temperature -40°C | ||
Pin Count 84 | ||
Maximum Operating Temperature 95°C | ||
Height 0.6mm | ||
Standards/Approvals RoHS | ||
Length 12.5mm | ||
Series W9751G6NB | ||
Width 8 mm | ||
Minimum Supply Voltage 1.7V | ||
Automotive Standard No | ||
Maximum Supply Voltage 1.9V | ||
The Winbond SDRAM is a 512M bits DDR2 SDRAM which is organized as 8,388,608 words, 4 banks, 16 bits. This device achieves high speed transfer rates for various applications.
Two data transfers per clock cycle
Edge-aligned with read data and centre-aligned with write data
DLL aligns DQ and DQS transitions with clock
관련된 링크들
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