Nexperia 74HCT573D,653 8-Bit D Type Latch, Transparent, 3 State, 20-Pin SO
- RS 제품 번호:
- 170-7988
- 제조사 부품 번호:
- 74HCT573D,653
- 제조업체:
- Nexperia
대량 구매 할인 기용 가능
Subtotal (1 reel of 2000 units)*
₩902,400.00
현재 액세스할 수 없는 재고 정보 - 나중에 다시 확인해 주세요.
수량 | 한팩당 | 릴당* |
|---|---|---|
| 2000 - 2000 | ₩451.20 | ₩900,520.00 |
| 4000 - 8000 | ₩441.80 | ₩882,472.00 |
| 10000 - 18000 | ₩428.64 | ₩856,152.00 |
| 20000 + | ₩419.24 | ₩838,856.00 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 170-7988
- 제조사 부품 번호:
- 74HCT573D,653
- 제조업체:
- Nexperia
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Nexperia | |
| Logic Family | 74HCT | |
| Product Type | D Type Latch | |
| Latch Mode | Transparent | |
| Logic Function | D Type | |
| Number of Bits | 8 | |
| Number of Channels | 8 | |
| Output Type | 3 State | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Minimum Supply Voltage | 4.5V | |
| Package Type | SO | |
| Maximum Supply Voltage | 5.5V | |
| Pin Count | 20 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 125°C | |
| Height | 2.45mm | |
| Width | 7.6 mm | |
| Series | 74HCT | |
| Standards/Approvals | No | |
| Length | 13mm | |
| Automotive Standard | No | |
| 모두 선택 | ||
|---|---|---|
브랜드 Nexperia | ||
Logic Family 74HCT | ||
Product Type D Type Latch | ||
Latch Mode Transparent | ||
Logic Function D Type | ||
Number of Bits 8 | ||
Number of Channels 8 | ||
Output Type 3 State | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Minimum Supply Voltage 4.5V | ||
Package Type SO | ||
Maximum Supply Voltage 5.5V | ||
Pin Count 20 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 125°C | ||
Height 2.45mm | ||
Width 7.6 mm | ||
Series 74HCT | ||
Standards/Approvals No | ||
Length 13mm | ||
Automotive Standard No | ||
The 74HC573, 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state.
Mixed 5 V and 3.3 V applications
Save board space
Low cost interface solutions
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant
Source termination
Low input threshold
CMOS low power
Key applications
Memory controllers
Backplane interfaces
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