Nexperia Octal D Type Latch, 8-Bit Non-Inverting, 20-Pin SO
- RS 제품 번호:
- 170-4869
- 제조사 부품 번호:
- 74HCT373D,653
- 제조업체:
- Nexperia
본 이미지는 참조용이오니 재확인이 필요하시면 문의해주세요.
대량 구매 할인 기용 가능
Subtotal (1 reel of 2000 units)*
₩763,280.00
재고있음
- 2,000 개 단위 배송 준비 완료
더 자세한 내용이 필요하신가요? 필요한 수량을 입력하고 '배송일 확인'을 클릭하면 더 많은 재고 및 배송 세부정보를 확인하실 수 있습니다.
수량 | 한팩당 | 릴당* |
|---|---|---|
| 2000 - 2000 | ₩381.64 | ₩763,656.00 |
| 4000 + | ₩366.60 | ₩733,200.00 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 170-4869
- 제조사 부품 번호:
- 74HCT373D,653
- 제조업체:
- Nexperia
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Nexperia | |
| Product Type | Octal D Type Latch | |
| Logic Family | 74HCT | |
| Logic Function | D Type | |
| Number of Channels | 8 | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Package Type | SO | |
| Minimum Supply Voltage | 4.5V | |
| Pin Count | 20 | |
| Input Level | TTL | |
| Maximum Supply Voltage | 5.5V | |
| Maximum Propagation Delay Time @ CL | 45ns | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 125°C | |
| Height | 2.45mm | |
| Standards/Approvals | No | |
| Series | 74HCT | |
| Length | 13mm | |
| Automotive Standard | No | |
| Output Type | 3 State | |
| 모두 선택 | ||
|---|---|---|
브랜드 Nexperia | ||
Product Type Octal D Type Latch | ||
Logic Family 74HCT | ||
Logic Function D Type | ||
Number of Channels 8 | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Package Type SO | ||
Minimum Supply Voltage 4.5V | ||
Pin Count 20 | ||
Input Level TTL | ||
Maximum Supply Voltage 5.5V | ||
Maximum Propagation Delay Time @ CL 45ns | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 125°C | ||
Height 2.45mm | ||
Standards/Approvals No | ||
Series 74HCT | ||
Length 13mm | ||
Automotive Standard No | ||
Output Type 3 State | ||
- COO (Country of Origin):
- CN
The 74HC373, 74HCT373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE.
Mixed 5 V and 3.3 V applications
Save board space
Low cost interface solutions
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant
Source termination
Low input threshold
CMOS low power
Key applications
Memory controllers
Backplane interfaces
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