Nexperia 74HCT165D,653 8-stage Surface Mount Shift Register 74HCT, 16-Pin SOIC
- RS 제품 번호:
- 170-8015
- 제조사 부품 번호:
- 74HCT165D,653
- 제조업체:
- Nexperia
대량 구매 할인 기용 가능
Subtotal (1 reel of 2500 units)*
₩831,900.00
일시적 품절
- 2026년 8월 03일 부터 배송
더 자세한 내용이 필요하신가요? 필요한 수량을 입력하고 '배송일 확인'을 클릭하면 더 많은 재고 및 배송 세부정보를 확인하실 수 있습니다.
수량 | 한팩당 | 릴당* |
|---|---|---|
| 2500 - 10000 | ₩332.76 | ₩830,490.00 |
| 12500 + | ₩298.92 | ₩747,300.00 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 170-8015
- 제조사 부품 번호:
- 74HCT165D,653
- 제조업체:
- Nexperia
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Nexperia | |
| Package Type | SO | |
| Logic Function | Shift Register | |
| Number of Stages | 8 | |
| Logic Family | 74HCT | |
| Mounting Type | Surface Mount | |
| Operation Mode | Serial, Parallel to Serial | |
| Number of Elements | 1 | |
| Pin Count | 16 | |
| Minimum Operating Supply Voltage | 4.5 V | |
| Maximum Operating Supply Voltage | 5.5 V | |
| Dimensions | 10 x 4 x 1.45mm | |
| Preset Type | Asynchronous, Synchronous | |
| Minimum Operating Temperature | -40 °C | |
| Triggering Type | Positive Edge | |
| Direction Type | Uni-Directional | |
| Maximum Operating Temperature | 125 °C | |
| 모두 선택 | ||
|---|---|---|
브랜드 Nexperia | ||
Package Type SO | ||
Logic Function Shift Register | ||
Number of Stages 8 | ||
Logic Family 74HCT | ||
Mounting Type Surface Mount | ||
Operation Mode Serial, Parallel to Serial | ||
Number of Elements 1 | ||
Pin Count 16 | ||
Minimum Operating Supply Voltage 4.5 V | ||
Maximum Operating Supply Voltage 5.5 V | ||
Dimensions 10 x 4 x 1.45mm | ||
Preset Type Asynchronous, Synchronous | ||
Minimum Operating Temperature -40 °C | ||
Triggering Type Positive Edge | ||
Direction Type Uni-Directional | ||
Maximum Operating Temperature 125 °C | ||
The 74HC165, 74HCT165 are high-speed Si-gate CMOS devices. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC165, 74HCT165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE) input.
Simple control interface
I/O expansion
Asynchronous and synchronous load options
High frequency
Cascadable
LED drivers
Key applications
Displays
Control units
I/O expansion
Asynchronous and synchronous load options
High frequency
Cascadable
LED drivers
Key applications
Displays
Control units
For these non-cancellable (NC), and non-returnable (NR) products, Terms and Conditions apply.
74HCT Family
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