Alliance Memory SDRAM 128 MB Surface, 54-Pin 16 bit TSOP
- RS 제품 번호:
- 230-8444P
- 제조사 부품 번호:
- AS4C8M16SA-7TCNTR
- 제조업체:
- Alliance Memory
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대량 구매 할인 기용 가능
View bulk pricing optionsSubtotal 50 units (supplied on a continuous strip)*
₩468,000.00
일시적 품절
- 2027년 1월 04일 부터 배송
더 자세한 내용이 필요하신가요? 필요한 수량을 입력하고 '배송일 확인'을 클릭하면 더 많은 재고 및 배송 세부정보를 확인하실 수 있습니다.
수량 | 한팩당 |
|---|---|
| 50 - 98 | ₩9,360.00 |
| 100 - 248 | ₩9,090.00 |
| 250 - 498 | ₩8,800.00 |
| 500 + | ₩8,550.00 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 230-8444P
- 제조사 부품 번호:
- AS4C8M16SA-7TCNTR
- 제조업체:
- Alliance Memory
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Alliance Memory | |
| Product Type | SDRAM | |
| Memory Size | 128MB | |
| Organisation | 8M x 16 bit | |
| Data Bus Width | 16bit | |
| Address Bus Width | 121bit | |
| Maximum Clock Frequency | 166MHz | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 5.4ns | |
| Number of Words | 2M | |
| Mount Type | Surface | |
| Package Type | TSOP | |
| Minimum Operating Temperature | 0°C | |
| Pin Count | 54 | |
| Maximum Operating Temperature | 70°C | |
| Height | 1.2mm | |
| Standards/Approvals | No | |
| Width | 8.1mm | |
| Series | AS4C8M16SA | |
| Length | 22.35mm | |
| Maximum Supply Voltage | 3.6V | |
| Minimum Supply Voltage | 3V | |
| Automotive Standard | No | |
| 모두 선택 | ||
|---|---|---|
브랜드 Alliance Memory | ||
Product Type SDRAM | ||
Memory Size 128MB | ||
Organisation 8M x 16 bit | ||
Data Bus Width 16bit | ||
Address Bus Width 121bit | ||
Maximum Clock Frequency 166MHz | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 5.4ns | ||
Number of Words 2M | ||
Mount Type Surface | ||
Package Type TSOP | ||
Minimum Operating Temperature 0°C | ||
Pin Count 54 | ||
Maximum Operating Temperature 70°C | ||
Height 1.2mm | ||
Standards/Approvals No | ||
Width 8.1mm | ||
Series AS4C8M16SA | ||
Length 22.35mm | ||
Maximum Supply Voltage 3.6V | ||
Minimum Supply Voltage 3V | ||
Automotive Standard No | ||
The Alliance Memory 128Mb SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V 0.3V power supply
Interface: LVTTL
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