Alliance Memory SDRAM 64 MB Surface, 54-Pin 16 bit TSOP
- RS Stock No.:
- 230-8434P
- Mfr. Part No.:
- AS4C4M16SA-7TCN
- Brand:
- Alliance Memory
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Subtotal 10 units (supplied in a tray)*
₩37,186.40
재고있음
- 10 개 단위 배송 준비 완료
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Units | Per unit |
|---|---|
| 10 - 20 | ₩3,718.64 |
| 25 - 45 | ₩3,654.72 |
| 50 - 70 | ₩3,590.80 |
| 75 + | ₩3,526.88 |
*price indicative
- RS Stock No.:
- 230-8434P
- Mfr. Part No.:
- AS4C4M16SA-7TCN
- Brand:
- Alliance Memory
Specifications
Technical Reference
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| 브랜드 | Alliance Memory | |
| Memory Size | 64MB | |
| Product Type | SDRAM | |
| Organisation | 4M x 16 bit | |
| Data Bus Width | 16bit | |
| Address Bus Width | 12bit | |
| Maximum Clock Frequency | 166MHz | |
| Number of Bits per Word | 16 | |
| Maximum Random Access Time | 5.4ns | |
| Number of Words | 1M | |
| Mount Type | Surface | |
| Package Type | TSOP | |
| Minimum Operating Temperature | 0°C | |
| Pin Count | 54 | |
| Maximum Operating Temperature | 70°C | |
| Series | AS4C4M16SA-C&I | |
| Length | 22.35mm | |
| Standards/Approvals | No | |
| Height | 1.2mm | |
| Width | 22.35 mm | |
| Automotive Standard | No | |
| Maximum Supply Voltage | 3.6V | |
| Minimum Supply Voltage | 3V | |
| Select all | ||
|---|---|---|
브랜드 Alliance Memory | ||
Memory Size 64MB | ||
Product Type SDRAM | ||
Organisation 4M x 16 bit | ||
Data Bus Width 16bit | ||
Address Bus Width 12bit | ||
Maximum Clock Frequency 166MHz | ||
Number of Bits per Word 16 | ||
Maximum Random Access Time 5.4ns | ||
Number of Words 1M | ||
Mount Type Surface | ||
Package Type TSOP | ||
Minimum Operating Temperature 0°C | ||
Pin Count 54 | ||
Maximum Operating Temperature 70°C | ||
Series AS4C4M16SA-C&I | ||
Length 22.35mm | ||
Standards/Approvals No | ||
Height 1.2mm | ||
Width 22.35 mm | ||
Automotive Standard No | ||
Maximum Supply Voltage 3.6V | ||
Minimum Supply Voltage 3V | ||
The Alliance Memory 64Mb SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured as 4 Banks of 1M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a Bank Activate command which is then followed by a Read or Write command.
Fast access time from clock: 4.5/5.4/5.4 ns
Fast clock rate: 200/166/143 MHz
Fully synchronous operation
Internal pipelined architecture
1M word x 16-bit x 4-bank