제조사부품번호

Alliance Memory AS4C16M16SA-7TCN SDRAM 256 MB Surface, 54-Pin 16 bit TSOP

RS 제품 번호:: 230-8420
Distrelec 제품 번호:: 304-31-278
제조사 부품 번호:: AS4C16M16SA-7TCN
제조업체:: Alliance Memory

Alliance Memory AS4C16M16SA-7TCN SDRAM 256 MB Surface, 54-Pin 16 bit TSOP

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대량 구매 할인 기용 가능

Subtotal (1 pack of 2 units)*

₩11,825.20

현재 액세스할 수 없는 재고 정보

수량	한팩당	한팩당*
2 - 8	₩5,912.60	₩11,825.20
10 - 18	₩5,809.20	₩11,618.40
20 - 48	₩5,705.80	₩11,411.60
50 - 98	₩5,593.00	₩11,186.00
100 +	₩5,499.00	₩10,998.00

* 참고 가격: 실제 구매가격과 다를 수 있습니다

RS 제품 번호:: 230-8420
Distrelec 제품 번호:: 304-31-278
제조사 부품 번호:: AS4C16M16SA-7TCN
제조업체:: Alliance Memory

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모두 선택	제품 정보	값
	브랜드	Alliance Memory
	Product Type	SDRAM
	Memory Size	256MB
	Organisation	16M x 16 Bit
	Data Bus Width	16bit
	Address Bus Width	13bit
	Number of Bits per Word	16
	Maximum Clock Frequency	166MHz
	Maximum Random Access Time	5.4ns
	Number of Words	4M
	Mount Type	Surface
	Package Type	TSOP
	Pin Count	54
	Minimum Operating Temperature	0°C
	Maximum Operating Temperature	70°C
	Width	10.29 mm
	Series	AS4C16M16SA-C&I
	Standards/Approvals	No
	Height	1.2mm
	Length	22.35mm
	Automotive Standard	No
	Minimum Supply Voltage	3V
	Maximum Supply Voltage	3.6V
	Supply Current	60mA

	모두 선택
	브랜드 Alliance Memory
	Product Type SDRAM
	Memory Size 256MB
	Organisation 16M x 16 Bit
	Data Bus Width 16bit
	Address Bus Width 13bit
	Number of Bits per Word 16
	Maximum Clock Frequency 166MHz
	Maximum Random Access Time 5.4ns
	Number of Words 4M
	Mount Type Surface
	Package Type TSOP
	Pin Count 54
	Minimum Operating Temperature 0°C
	Maximum Operating Temperature 70°C
	Width 10.29 mm
	Series AS4C16M16SA-C&I
	Standards/Approvals No
	Height 1.2mm
	Length 22.35mm
	Automotive Standard No
	Minimum Supply Voltage 3V
	Maximum Supply Voltage 3.6V
	Supply Current 60mA

Datasheet - AS4C16M16SA-7TCN

The Alliance Memory 256Mb SDRAM is a high-speed CMOS synchronous DRAM containing 256 Mbits. It is internally configured as 4 Banks of 4M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.

Fast access time from clock: 5/5.4 ns

Fast clock rate: 166/143 MHz

Fully synchronous operation

Internal pipelined architecture

4M word x 16-bit x 4-bank

Alliance Memory AS4C16M16SA-7TCN SDRAM 256 MB Surface, 54-Pin 16 bit TSOP

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