Renesas Electronics 9DB102BGILF, LVDS Buffer Dual TTL Buffer, 20-Pin TSSOP
- RS 제품 번호:
- 217-7929
- 제조사 부품 번호:
- 9DB102BGILF
- 제조업체:
- Renesas Electronics
대량 구매 할인 기용 가능
Subtotal (1 pack of 5 units)*
₩31,997.60
재고있음
- 추가로 2025년 12월 29일 부터 120 개 단위 배송
더 자세한 내용이 필요하신가요? 필요한 수량을 입력하고 '배송일 확인'을 클릭하면 더 많은 재고 및 배송 세부정보를 확인하실 수 있습니다.
수량 | 한팩당 | 한팩당* |
|---|---|---|
| 5 - 15 | ₩6,399.52 | ₩31,997.60 |
| 20 - 30 | ₩6,241.60 | ₩31,208.00 |
| 35 + | ₩6,143.84 | ₩30,719.20 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 217-7929
- 제조사 부품 번호:
- 9DB102BGILF
- 제조업체:
- Renesas Electronics
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Renesas Electronics | |
| Number of Drivers | 2 | |
| Input Type | TTL | |
| Output Type | Buffer | |
| Number of Elements per Chip | 2 | |
| Package Type | TSSOP | |
| Pin Count | 20 | |
| 모두 선택 | ||
|---|---|---|
브랜드 Renesas Electronics | ||
Number of Drivers 2 | ||
Input Type TTL | ||
Output Type Buffer | ||
Number of Elements per Chip 2 | ||
Package Type TSSOP | ||
Pin Count 20 | ||
The Renesas Electronics 9DB102 zero-delay buffer supports PCI Express clocking requirements. The 9DB102 is driven by a differential SRC output pair from an IDT CK409/CK410-compliant main clock generator such as the 952601 or 954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread- Spectrum clocking.
2 - 0.7 V HCSL differential output pairs
Phase jitter: PCIe Gen2 < 3.1 ps rms
Phase jitter: PCIe Gen1 < 86 ps peak to peak
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
33-110 MHz operation in PLL mode
10-110 MHz operation in Bypass mode
Phase jitter: PCIe Gen2 < 3.1 ps rms
Phase jitter: PCIe Gen1 < 86 ps peak to peak
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
33-110 MHz operation in PLL mode
10-110 MHz operation in Bypass mode
For these non-cancellable (NC), and non-returnable (NR) products, Terms and Conditions apply.
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