Nexperia HEF4071BT,653, 4 2-Input OR Gate Logic Gate, 14-Pin SO-14
- RS 제품 번호:
- 625-398
- 제조사 부품 번호:
- HEF4071BT,653
- 제조업체:
- Nexperia
대량 구매 할인 기용 가능
Subtotal (1 unit)*
₩413.60
재고있음
- 2,461 개 단위 배송 준비 완료
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수량 | 한팩당 |
|---|---|
| 1 - 24 | ₩413.60 |
| 25 - 99 | ₩376.00 |
| 100 - 499 | ₩338.40 |
| 500 - 999 | ₩282.00 |
| 1000 + | ₩225.60 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 625-398
- 제조사 부품 번호:
- HEF4071BT,653
- 제조업체:
- Nexperia
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Nexperia | |
| Logic Function | OR Gate | |
| Product Type | Logic Gate | |
| Mount Type | Surface | |
| Number of Elements | 4 | |
| Number of Inputs per Gate | 2 | |
| Schmitt Trigger Input | No | |
| Package Type | SO-14 | |
| Pin Count | 14 | |
| Logic Family | CMOS | |
| Maximum High Level Output Current | -4.2mA | |
| Minimum Operating Temperature | -40°C | |
| Maximum Propagation Delay Time @ CL | 120ns | |
| Maximum Operating Temperature | 125°C | |
| Standards/Approvals | JEDEC JESD 13-B | |
| Length | 8.75mm | |
| Maximum Supply Voltage | 18V | |
| Series | HEF4071B | |
| Minimum Supply Voltage | 3V | |
| Width | 3.9 mm | |
| Maximum Low Level Output Current | 4.2mA | |
| Automotive Standard | No | |
| Output Type | Standard | |
| 모두 선택 | ||
|---|---|---|
브랜드 Nexperia | ||
Logic Function OR Gate | ||
Product Type Logic Gate | ||
Mount Type Surface | ||
Number of Elements 4 | ||
Number of Inputs per Gate 2 | ||
Schmitt Trigger Input No | ||
Package Type SO-14 | ||
Pin Count 14 | ||
Logic Family CMOS | ||
Maximum High Level Output Current -4.2mA | ||
Minimum Operating Temperature -40°C | ||
Maximum Propagation Delay Time @ CL 120ns | ||
Maximum Operating Temperature 125°C | ||
Standards/Approvals JEDEC JESD 13-B | ||
Length 8.75mm | ||
Maximum Supply Voltage 18V | ||
Series HEF4071B | ||
Minimum Supply Voltage 3V | ||
Width 3.9 mm | ||
Maximum Low Level Output Current 4.2mA | ||
Automotive Standard No | ||
Output Type Standard | ||
- COO (Country of Origin):
- CN
The Nexperia Quad 2-input OR gate is designed with input clamp diodes, allowing the use of current limiting resistors to safely interface with input voltages higher than VDD. It provides standard OR logic functionality across four independent gates.
Fully static operation
CMOS low power dissipation
High noise immunity
Standardized symmetrical output characteristics
Inputs and outputs are protected against electrostatic effects
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