Lattice FPGA ICE40HX4K-TQ144, iCE40 HX 3520 Cells, 80kbit, 440 Blocks, 144-Pin TQFP
- RS 제품 번호:
- 168-4222
- 제조사 부품 번호:
- ICE40HX4K-TQ144
- 제조업체:
- Lattice Semiconductor
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대량 구매 할인 기용 가능
Subtotal (1 tray of 60 units)*
₩984,405.60
재고있음
- 420 개 단위 배송 준비 완료
더 자세한 내용이 필요하신가요? 필요한 수량을 입력하고 '배송일 확인'을 클릭하면 더 많은 재고 및 배송 세부정보를 확인하실 수 있습니다.
수량 | 한팩당 | Per Tray* |
|---|---|---|
| 60 - 240 | ₩16,406.76 | ₩984,405.60 |
| 300 + | ₩16,077.76 | ₩964,699.44 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 168-4222
- 제조사 부품 번호:
- ICE40HX4K-TQ144
- 제조업체:
- Lattice Semiconductor
사양
참조 문서
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제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Lattice Semiconductor | |
| Family Name | iCE40 HX | |
| Number of Logic Cells | 3520 | |
| Number of Logic Units | 440 | |
| Number of Registers | 3520 | |
| Mounting Type | Surface Mount | |
| Package Type | TQFP | |
| Pin Count | 144 | |
| Number of RAM Bits | 80kbit | |
| Dimensions | 20 x 20 x 1.45mm | |
| Height | 1.45mm | |
| Length | 20mm | |
| Width | 20mm | |
| Maximum Operating Temperature | +85 °C | |
| Minimum Operating Temperature | -40 °C | |
| Minimum Operating Supply Voltage | 1.14 V | |
| Maximum Operating Supply Voltage | 1.26 V | |
| 모두 선택 | ||
|---|---|---|
브랜드 Lattice Semiconductor | ||
Family Name iCE40 HX | ||
Number of Logic Cells 3520 | ||
Number of Logic Units 440 | ||
Number of Registers 3520 | ||
Mounting Type Surface Mount | ||
Package Type TQFP | ||
Pin Count 144 | ||
Number of RAM Bits 80kbit | ||
Dimensions 20 x 20 x 1.45mm | ||
Height 1.45mm | ||
Length 20mm | ||
Width 20mm | ||
Maximum Operating Temperature +85 °C | ||
Minimum Operating Temperature -40 °C | ||
Minimum Operating Supply Voltage 1.14 V | ||
Maximum Operating Supply Voltage 1.26 V | ||
- COO (Country of Origin):
- KR
Field Programmable Gate Arrays, Lattice Semiconductor
For these non-cancellable (NC), and non-returnable (NR) products, Terms and Conditions apply.
An FPGA is a semiconductor device consisting of a matrix of Configurable Logic Blocks (CLBs) connected through programmable interconnects. The user determines these interconnections by programming SRAM. A CLB can be simple (AND, OR gates, etc) or complex (a block of RAM). The FPGA allows changes to be made to a design even after the device is soldered into a PCB.
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