Nexperia 74LVC1G175GW,125 1 Flip Flop IC 74LVC, Single Ended, 6-Pin SC-88
- RS 제품 번호:
- 170-5470
- 제조사 부품 번호:
- 74LVC1G175GW,125
- 제조업체:
- Nexperia
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대량 구매 할인 기용 가능
Subtotal (1 pack of 100 units)*
₩10,530.00
현재 액세스할 수 없는 재고 정보 - 나중에 다시 확인해 주세요.
수량 | 한팩당 | 한팩당* |
|---|---|---|
| 100 - 700 | ₩105.30 | ₩10,549.50 |
| 800 - 1400 | ₩103.35 | ₩10,296.00 |
| 1500 + | ₩101.40 | ₩10,120.50 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 170-5470
- 제조사 부품 번호:
- 74LVC1G175GW,125
- 제조업체:
- Nexperia
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Nexperia | |
| Logic Family | 74LVC | |
| Product Type | Flip Flop IC | |
| Input Type | Single Ended | |
| Output Type | Single Ended | |
| Clock Frequency | 200MHz | |
| Polarity | Non-Inverting | |
| Mount Type | Surface | |
| Package Type | SC-88 | |
| Minimum Supply Voltage | 1.65V | |
| Pin Count | 6 | |
| Maximum Supply Voltage | 5.5V | |
| Flip-Flop Type | D Flip-Flop | |
| Trigger Type | Positive Edge | |
| Minimum Operating Temperature | -40°C | |
| Maximum Propagation Delay Time @ CL | 5.5ns | |
| Number of Elements per Chip | 1 | |
| Maximum Operating Temperature | 125°C | |
| Standards/Approvals | No | |
| Length | 2.2mm | |
| Height | 1mm | |
| Automotive Standard | No | |
| 모두 선택 | ||
|---|---|---|
브랜드 Nexperia | ||
Logic Family 74LVC | ||
Product Type Flip Flop IC | ||
Input Type Single Ended | ||
Output Type Single Ended | ||
Clock Frequency 200MHz | ||
Polarity Non-Inverting | ||
Mount Type Surface | ||
Package Type SC-88 | ||
Minimum Supply Voltage 1.65V | ||
Pin Count 6 | ||
Maximum Supply Voltage 5.5V | ||
Flip-Flop Type D Flip-Flop | ||
Trigger Type Positive Edge | ||
Minimum Operating Temperature -40°C | ||
Maximum Propagation Delay Time @ CL 5.5ns | ||
Number of Elements per Chip 1 | ||
Maximum Operating Temperature 125°C | ||
Standards/Approvals No | ||
Length 2.2mm | ||
Height 1mm | ||
Automotive Standard No | ||
The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, Master reset (MR) input, and Q output. The Master reset (MR) is an asynchronous Active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Mixed 5 V and 3.3 V applications
Improved signal integrity with integrated termination resistors
High noise immunity
Flow through pin out for easy layout
Wide supply voltage range
Low propagation delay
Overvoltage tolerant input options
Integrated source termination resistor options
Bus hold options
Frequency division
Controlled delays
Interface between asynchronous and synchronous systems
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