Nexperia 2 Flip Flop IC 74LVC, D Type, 14-Pin TSSOP
- RS 제품 번호:
- 170-4845
- 제조사 부품 번호:
- 74LVC74APW,118
- 제조업체:
- Nexperia
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대량 구매 할인 기용 가능
View bulk pricing optionsSubtotal (1 reel of 2500 units)*
₩516,750.00
일시적 품절
- 2026년 12월 14일 부터 배송
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수량 | 한팩당 | 릴당* |
|---|---|---|
| 2500 - 2500 | ₩206.70 | ₩515,287.50 |
| 5000 - 7500 | ₩202.80 | ₩505,050.00 |
| 10000 + | ₩198.90 | ₩494,812.50 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 170-4845
- 제조사 부품 번호:
- 74LVC74APW,118
- 제조업체:
- Nexperia
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Nexperia | |
| Logic Family | 74LVC | |
| Product Type | Flip Flop IC | |
| Input Type | Single Ended | |
| Output Type | D Type | |
| Clock Frequency | 120MHz | |
| Polarity | Inverting, Non-Inverting | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Minimum Supply Voltage | 1.65V | |
| Pin Count | 14 | |
| Maximum Supply Voltage | 3.6V | |
| Minimum Operating Temperature | -40°C | |
| Flip-Flop Type | D Flip-Flop | |
| Maximum Propagation Delay Time @ CL | 6.5ns | |
| Trigger Type | Positive Edge | |
| Maximum Operating Temperature | 125°C | |
| Number of Elements per Chip | 2 | |
| Standards/Approvals | No | |
| Height | 0.95mm | |
| Length | 5.1mm | |
| Automotive Standard | No | |
| 모두 선택 | ||
|---|---|---|
브랜드 Nexperia | ||
Logic Family 74LVC | ||
Product Type Flip Flop IC | ||
Input Type Single Ended | ||
Output Type D Type | ||
Clock Frequency 120MHz | ||
Polarity Inverting, Non-Inverting | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Minimum Supply Voltage 1.65V | ||
Pin Count 14 | ||
Maximum Supply Voltage 3.6V | ||
Minimum Operating Temperature -40°C | ||
Flip-Flop Type D Flip-Flop | ||
Maximum Propagation Delay Time @ CL 6.5ns | ||
Trigger Type Positive Edge | ||
Maximum Operating Temperature 125°C | ||
Number of Elements per Chip 2 | ||
Standards/Approvals No | ||
Height 0.95mm | ||
Length 5.1mm | ||
Automotive Standard No | ||
- COO (Country of Origin):
- CN
The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous Active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.
Mixed 5 V and 3.3 V applications
Improved signal integrity with integrated termination resistors
High noise immunity
Flow through pin out for easy layout
Wide supply voltage range
Low propagation delay
Overvoltage tolerant input options
Integrated source termination resistor options
Bus hold options
Frequency division
Controlled delays
Interface between asynchronous and synchronous systems
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