Infineon NOR 8Mbit CFI Flash Memory 48-Pin TSOP, S29AL008J70TFI013
- RS 제품 번호:
- 193-8785
- 제조사 부품 번호:
- S29AL008J70TFI013
- 제조업체:
- Infineon
대량 구매 할인 기용 가능
Subtotal (1 pack of 5 units)*
₩18,010.40
마지막 RS 재고
- 최종적인 970 개 unit(s)이 배송 준비 됨
수량 | 한팩당 | 한팩당* |
|---|---|---|
| 5 - 245 | ₩3,602.08 | ₩18,010.40 |
| 250 - 495 | ₩3,523.12 | ₩17,615.60 |
| 500 + | ₩3,444.16 | ₩17,220.80 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 193-8785
- 제조사 부품 번호:
- S29AL008J70TFI013
- 제조업체:
- Infineon
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Infineon | |
| Memory Size | 8Mbit | |
| Interface Type | CFI | |
| Package Type | TSOP | |
| Pin Count | 48 | |
| Organisation | 1M x 8 bit | |
| Mounting Type | Surface Mount | |
| Cell Type | NOR | |
| Minimum Operating Supply Voltage | 2.7 V | |
| Maximum Operating Supply Voltage | 3.6 V | |
| Block Organisation | Asymmetrical | |
| Length | 12mm | |
| Height | 1.05mm | |
| Width | 18.4mm | |
| Dimensions | 18.4 x 12 x 1.05mm | |
| Maximum Operating Temperature | +85 °C | |
| Automotive Standard | AEC-Q100 | |
| Maximum Random Access Time | 70ns | |
| Number of Words | 1M | |
| Number of Bits per Word | 8bit | |
| Minimum Operating Temperature | -40 °C | |
| Series | S29AL | |
| 모두 선택 | ||
|---|---|---|
브랜드 Infineon | ||
Memory Size 8Mbit | ||
Interface Type CFI | ||
Package Type TSOP | ||
Pin Count 48 | ||
Organisation 1M x 8 bit | ||
Mounting Type Surface Mount | ||
Cell Type NOR | ||
Minimum Operating Supply Voltage 2.7 V | ||
Maximum Operating Supply Voltage 3.6 V | ||
Block Organisation Asymmetrical | ||
Length 12mm | ||
Height 1.05mm | ||
Width 18.4mm | ||
Dimensions 18.4 x 12 x 1.05mm | ||
Maximum Operating Temperature +85 °C | ||
Automotive Standard AEC-Q100 | ||
Maximum Random Access Time 70ns | ||
Number of Words 1M | ||
Number of Bits per Word 8bit | ||
Minimum Operating Temperature -40 °C | ||
Series S29AL | ||
- COO (Country of Origin):
- TH
The S29AL008J is a 8 Mbit, 3.0 Volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball Fine-pitch BGA (0.8 mm pitch) and 48pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0, the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. A 12.0 V VPP or 5.0 VCC are not required for write or erase operations. The device can also be programmed in standard EPROM programmers.
The device offers access times of up to 55 ns allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. Duringerase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7(Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
The device offers access times of up to 55 ns allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. Duringerase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7(Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
For these non-cancellable (NC), and non-returnable (NR) products, Terms and Conditions apply.
관련된 링크들
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