Microchip, 16 bit Digital Signal Processor 70 MIPS 256kB FLASH 28-Pin PDIP

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Subtotal (1 tube of 15 units)*

₩127,617.75

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Per Tube*
15 - 15₩8,507.85₩127,627.50
30 - 45₩8,338.20₩125,073.00
60 +₩8,170.50₩122,557.50

* 참고 가격: 실제 구매가격과 다를 수 있습니다

RS 제품 번호:
178-4849
제조사 부품 번호:
DSPIC33EV256GM102-I/SP
제조업체:
Microchip
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브랜드

Microchip

Product Type

Digital Signal Processor

Maximum Clock Frequency

70MIPS

Device Million Instructions per Second

70MIPS

Data Bus Width

16bit

RAM Size

16kB

Instruction Set Architecture

Code Efficient

Program Memory Size

256kB

Program Memory Type

FLASH

Minimum Supply Voltage

4.5V

Maximum Supply Voltage

3.6V

Mount Type

Through Hole

Package Type

PDIP

Minimum Operating Temperature

-40°C

Number of PWM Channels

6

Number of ADCs

1

Maximum Operating Temperature

85°C

Pin Count

28

Height

3.81mm

Length

35.56mm

Standards/Approvals

No

ADC Resolution

19bit

Automotive Standard

AEC-Q100

Timer Resolution

32bit

PWM Resolution

16bit

Number of PWM Units

1

ADC Channels

11

dsPIC33EVxxxGM00x/10x 16-Bit Digital Signal Controllers


Microchip’s dsPIC33EV family of 16-bit Digital Signal Controllers (DSCs) features a 70 MIPS dsPIC® DSC core with enhanced on-chip features. Capable of operating in harsh environments these devices are suitable for appliance and automotive applications. Rich peripheral integration includes SENT (Single-Edge Nibble Transmission-Transmit/Receive), High Speed PWMs, OP Amps and Error Correcting Code Flash for increased reliability and safety. The performance offered by the dsPIC33EV family of MCUs allows them to be incorporated into the design of high-performance, precision motor control systems that are more energy efficient. They can be used to control BLDC, permanent magnet synchronous, AC induction and stepper motors.

Microcontroller Features


70 MHz Max. CPU Speed

Code-Efficient (C and Assembly) Architecture

16-Bit Wide Data Path

Two 40-Bit Wide Accumulators

Single-Cycle (MAC/MPY) with Dual Data Fetch

Single-Cycle, Mixed-Sign MUL plus Hardware Divide

32-Bit Multiply Support

Intermediate Security for Memory - Provides a Boot Flash Segment in addition to the existing General Flash Segment

Error Code Correction (ECC) for Flash

Added Two Alternate Register Sets for Fast Context Switching

Clock Management Features


Internal, 15% Low-Power RC (LPRC) – 32 kHz

Internal, 1% Fast RC (FRC) – 7.37 MHz

Internal, 10% Backup RC (BFRC) – 7.37 MHz

Programmable PLLs and Oscillator Clock Sources

Fail-Safe Clock Monitor (FSCM)

Additional Fail-Safe Clock Monitor Source (BFRC), Intended to Provide a Clock Fail Switch Source for the System Clock

Independent Watchdog Timer (WDT)

System Windowed Watchdog Timer (DMT)

Fast Wake-Up and Start-Up

Power Management Features


Low-Power Management modes (Sleep, Idle and Doze)

Power Consumption Minimized Executing NOP String

Integrated Power-on Reset (POR) and Brown-out Reset (BOR)

0.5 mA/MHz Dynamic Current (typical)

50 μA at +25°C IPD Current (typical)

Peripheral Features


Up to Six Pulse-Width Modulation (PWM) Outputs (three generators)

Configurable Analogue to Digital Converter (ADC) Module

Up to 4 Operational Amplifiers

Up to 5 Comparators

Charge Time Measurement Unit (CTMU) - Supports mTouch™ capacitive touch sensing

Five 16-bit Timers

Two 32-bit Timers

Four Output Capture modules Configurable as Timers/Counters

Four Input Capture modules

Two Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)

Two SPI Modules

One I2C Module with SMBus Support

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