Renesas Electronics RC32504A000GNK#BB0 Frequency Synthesiser 8 24-Pin 5.5 V QFN-24
- RS 제품 번호:
- 230-6594
- 제조사 부품 번호:
- RC32504A000GNK#BB0
- 제조업체:
- Renesas Electronics
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현재 비가용
RS는 이 제품을 더 이상 판매하지 않습니다.
- RS 제품 번호:
- 230-6594
- 제조사 부품 번호:
- RC32504A000GNK#BB0
- 제조업체:
- Renesas Electronics
사양
참조 문서
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제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Renesas Electronics | |
| Product Type | Frequency Synthesiser | |
| Conversion Rate | 20Gsps | |
| Maximum Output Frequency | 180MHz | |
| Mount Type | Surface | |
| Package Type | QFN-24 | |
| Pin Count | 24 | |
| Minimum Supply Voltage | 2.3V | |
| Maximum Supply Voltage | 5.5V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Height | 0.9mm | |
| Length | 4mm | |
| Standards/Approvals | RoHS | |
| Automotive Standard | No | |
| 모두 선택 | ||
|---|---|---|
브랜드 Renesas Electronics | ||
Product Type Frequency Synthesiser | ||
Conversion Rate 20Gsps | ||
Maximum Output Frequency 180MHz | ||
Mount Type Surface | ||
Package Type QFN-24 | ||
Pin Count 24 | ||
Minimum Supply Voltage 2.3V | ||
Maximum Supply Voltage 5.5V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Height 0.9mm | ||
Length 4mm | ||
Standards/Approvals RoHS | ||
Automotive Standard No | ||
The Renesas Electronics RC32504A universal frequency translator is a small, low-power timing component designed to be placed immediately adjacent to a PHY, switch, ASIC or FPGA that requires several reference clocks with jitter performance less than 100fs. It can act as a frequency synthesizer to locally generate the reference clock, a jitter attenuator to perform local clean-up and/or frequency translation of a centrally-supplied reference, a Synchronous Ethernet equipment clock to perform passband filtering and clean-up of network-supplied references or as a DCO for frequency margining or OTN clock applications.
Jitter below 100fs RMS (10kHz to 20MHz)
Compliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for enhanced synchronous Ethernet/OTN (eEEC/eOEC)
PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Digital PLL (DPLL)
Programmable input buffer supports HCSL, LVDS, or two LVCMOS with no external terminations needed
Reference monitor qualifies/disqualifies input clock
Programmable status output
Supports up to 1MHz I2C or up to 20MHz SPI serial processor port
Can configure itself automatically after reset through internal customer-definable One-Time Programmable (OTP) memory with up to four different configurations
4 x 4 mm 24-QFN package
4 differential/8 LVCMOS outputs
Output Enable input with programmable effect
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