85104AGILF, Clock Buffer, 5-Input, 20-Pin TSSOP
- RS 제품 번호:
- 216-6209
- 제조사 부품 번호:
- 85104AGILF
- 제조업체:
- Renesas Electronics
대량 구매 할인 기용 가능
Subtotal (1 tube of 74 units)*
₩1,766,267.52
마지막 RS 재고
- 최종적인 222 개 unit(s)이 배송 준비 됨
수량 | 한팩당 | Per Tube* |
|---|---|---|
| 74 - 74 | ₩23,868.48 | ₩1,766,226.16 |
| 148 - 222 | ₩23,390.96 | ₩1,730,902.84 |
| 296 + | ₩22,922.84 | ₩1,696,290.16 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 216-6209
- 제조사 부품 번호:
- 85104AGILF
- 제조업체:
- Renesas Electronics
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Renesas Electronics | |
| Logic Function | Clock Buffer | |
| Number of Clock Inputs | 5 | |
| Package Type | TSSOP | |
| Pin Count | 20 | |
| 모두 선택 | ||
|---|---|---|
브랜드 Renesas Electronics | ||
Logic Function Clock Buffer | ||
Number of Clock Inputs 5 | ||
Package Type TSSOP | ||
Pin Count 20 | ||
The Renesas Electronics 85104I is a low skew, high performance 1-to-4 Differential/LVCMOS-to-0.7V HCSL Fanout Buffer. The 85104I has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
Four 0.7V differential HCSL outputs
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 100ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximum)
Additive phase jitter, RMS: 0.22ps (typical)
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 100ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximum)
Additive phase jitter, RMS: 0.22ps (typical)
For these non-cancellable (NC), and non-returnable (NR) products, Terms and Conditions apply.
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