Renesas Electronics 9DB633AGILF Clock Buffer 28-Pin TSSOP
- RS 제품 번호:
- 263-7988
- 제조사 부품 번호:
- 9DB633AGILF
- 제조업체:
- Renesas Electronics
대량 구매 할인 기용 가능
Subtotal (1 unit)*
₩8,441.20
일시적 품절
- 2026년 4월 02일 부터 배송
더 자세한 내용이 필요하신가요? 필요한 수량을 입력하고 '배송일 확인'을 클릭하면 더 많은 재고 및 배송 세부정보를 확인하실 수 있습니다.
수량 | 한팩당 |
|---|---|
| 1 - 9 | ₩8,441.20 |
| 10 - 24 | ₩7,595.20 |
| 25 - 49 | ₩7,426.00 |
| 50 - 99 | ₩7,181.60 |
| 100 + | ₩6,241.60 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 263-7988
- 제조사 부품 번호:
- 9DB633AGILF
- 제조업체:
- Renesas Electronics
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Renesas Electronics | |
| Number of Elements per Chip | 5 | |
| Maximum Supply Current | 200 μA | |
| Maximum Input Frequency | 110MHz | |
| Mounting Type | Surface Mount | |
| Package Type | TSSOP | |
| Pin Count | 28 | |
| 모두 선택 | ||
|---|---|---|
브랜드 Renesas Electronics | ||
Number of Elements per Chip 5 | ||
Maximum Supply Current 200 μA | ||
Maximum Input Frequency 110MHz | ||
Mounting Type Surface Mount | ||
Package Type TSSOP | ||
Pin Count 28 | ||
- COO (Country of Origin):
- TW
The Renesas Electronics zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. It is driven by a differential SRC output pair from an IDT main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread-spectrum clocking.
SMBus Interface
Selectable PLL bandwidth
Minimizes jitter peaking in downstream PLLs
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
PCIe Gen3 phase jitter < 1.0ps RMS
Selectable PLL bandwidth
Minimizes jitter peaking in downstream PLLs
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
PCIe Gen3 phase jitter < 1.0ps RMS
For these non-cancellable (NC), and non-returnable (NR) products, Terms and Conditions apply.
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