Renesas Electronics 8305AGLF Clock Buffer, 16-Pin 4 TSSOP
- RS 제품 번호:
- 216-6206P
- 제조사 부품 번호:
- 8305AGLF
- 제조업체:
- Renesas Electronics
본 이미지는 참조용이오니 재확인이 필요하시면 문의해주세요.
대량 구매 할인 기용 가능
Subtotal 24 units (supplied in a tube)*
₩280,872.00
마지막 RS 재고
- 최종적인 148 개 unit(s)이 배송 준비 됨
수량 | 한팩당 |
|---|---|
| 24 - 46 | ₩11,703.00 |
| 48 + | ₩11,524.40 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 216-6206P
- 제조사 부품 번호:
- 8305AGLF
- 제조업체:
- Renesas Electronics
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Pin Count | 16 | |
| Minimum Supply Voltage | 1.5V | |
| Maximum Supply Voltage | 3.3V | |
| Minimum Operating Temperature | 0°C | |
| Maximum Operating Temperature | 70°C | |
| Standards/Approvals | No | |
| Series | 8305A | |
| Length | 4mm | |
| Width | 3.3 mm | |
| Height | 0.9mm | |
| Number of Outputs | 4 | |
| Automotive Standard | No | |
| 모두 선택 | ||
|---|---|---|
브랜드 Renesas Electronics | ||
Product Type Clock Buffer | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Pin Count 16 | ||
Minimum Supply Voltage 1.5V | ||
Maximum Supply Voltage 3.3V | ||
Minimum Operating Temperature 0°C | ||
Maximum Operating Temperature 70°C | ||
Standards/Approvals No | ||
Series 8305A | ||
Length 4mm | ||
Width 3.3 mm | ||
Height 0.9mm | ||
Number of Outputs 4 | ||
Automotive Standard No | ||
The Renesas Electronics ICS8305 is a low skew, 1-to-4, Differential/ LVCMOS-to-LVCMOS/LVTTL Fanout Buffer. The ICS8305 has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state.
Four LVCMOS / LVTTL outputs, 7 output impedance
Selectable differential or LVCMOS / LVTTL clock inputs
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
Maximum output frequency: 350MHz
Output skew: 35ps (maximum)
Part-to-part skew: 700ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)
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