Infineon Clock Buffer 8-Pin SOIC
- RS 제품 번호:
- 273-7327
- 제조사 부품 번호:
- CY2305SXI-1
- 제조업체:
- Infineon
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대량 구매 할인 기용 가능
Subtotal (1 unit)*
₩4,192.40
일시적 품절
- 61 개 단위 배송 준비 완료
더 자세한 내용이 필요하신가요? 필요한 수량을 입력하고 '배송일 확인'을 클릭하면 더 많은 재고 및 배송 세부정보를 확인하실 수 있습니다.
수량 | 한팩당 |
|---|---|
| 1 - 9 | ₩4,192.40 |
| 10 - 24 | ₩3,590.80 |
| 25 - 49 | ₩3,534.40 |
| 50 - 99 | ₩3,459.20 |
| 100 + | ₩3,346.40 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 273-7327
- 제조사 부품 번호:
- CY2305SXI-1
- 제조업체:
- Infineon
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Infineon | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 133MHz | |
| Maximum Propagation Delay Time | 8.7ns | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Number of Outputs | 8 | |
| Minimum Supply Voltage | 3V | |
| Maximum Supply Voltage | 3.6V | |
| Minimum Operating Temperature | 0°C | |
| Maximum Operating Temperature | 70°C | |
| Series | CY2305 | |
| Length | 5.84mm | |
| Width | 4.8 mm | |
| Standards/Approvals | No | |
| Height | 1.5mm | |
| Automotive Standard | No | |
| 모두 선택 | ||
|---|---|---|
브랜드 Infineon | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 133MHz | ||
Maximum Propagation Delay Time 8.7ns | ||
Mount Type Surface | ||
Package Type SOIC | ||
Pin Count 8 | ||
Number of Outputs 8 | ||
Minimum Supply Voltage 3V | ||
Maximum Supply Voltage 3.6V | ||
Minimum Operating Temperature 0°C | ||
Maximum Operating Temperature 70°C | ||
Series CY2305 | ||
Length 5.84mm | ||
Width 4.8 mm | ||
Standards/Approvals No | ||
Height 1.5mm | ||
Automotive Standard No | ||
The Infineon Zero delay buffer designed to distribute high speed clocks. It accepts one reference input and drives out five low skew clocks. All parts have on chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on chip and is obtained from the CLKOUT pad. This buffer devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps.
60 ps typical cycle to cycle jitter
Zero input output propagation delay
Test mode to bypass phase locked loop
Compatible with Pentium based systems
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