Infineon S27KL0642DPBHI020 SDRAM 64 MB Surface, 24-Pin 8 bit FBGA-24 Ball
- RS 제품 번호:
- 273-7513
- 제조사 부품 번호:
- S27KL0642DPBHI020
- 제조업체:
- Infineon
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대량 구매 할인 기용 가능
View bulk pricing optionsSubtotal (1 unit)*
₩7,680.00
마지막 RS 재고
- 최종적인 3 개 unit(s)이 배송 준비 됨
수량 | 한팩당 |
|---|---|
| 1 - 9 | ₩7,680.00 |
| 10 - 24 | ₩7,360.00 |
| 25 - 49 | ₩7,080.00 |
| 50 - 99 | ₩6,940.00 |
| 100 + | ₩6,720.00 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 273-7513
- 제조사 부품 번호:
- S27KL0642DPBHI020
- 제조업체:
- Infineon
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Infineon | |
| Product Type | SDRAM | |
| Memory Size | 64MB | |
| Data Bus Width | 8bit | |
| Number of Bits per Word | 16 | |
| Maximum Clock Frequency | 200MHz | |
| Mount Type | Surface | |
| Package Type | FBGA-24 Ball | |
| Pin Count | 24 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 105°C | |
| Height | 1mm | |
| Standards/Approvals | No | |
| Width | 8mm | |
| Series | S27K | |
| Length | 6mm | |
| Automotive Standard | AEC-Q100 Grade 2 & 3 | |
| Supply Current | 360μA | |
| Maximum Supply Voltage | 3.6V | |
| Minimum Supply Voltage | 1.8V | |
| 모두 선택 | ||
|---|---|---|
브랜드 Infineon | ||
Product Type SDRAM | ||
Memory Size 64MB | ||
Data Bus Width 8bit | ||
Number of Bits per Word 16 | ||
Maximum Clock Frequency 200MHz | ||
Mount Type Surface | ||
Package Type FBGA-24 Ball | ||
Pin Count 24 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 105°C | ||
Height 1mm | ||
Standards/Approvals No | ||
Width 8mm | ||
Series S27K | ||
Length 6mm | ||
Automotive Standard AEC-Q100 Grade 2 & 3 | ||
Supply Current 360μA | ||
Maximum Supply Voltage 3.6V | ||
Minimum Supply Voltage 1.8V | ||
The Infineon DRAM is a high speed CMOS, self refresh DRAM, with HYPERBUS interface. The DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS interface master. Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately described as Pseudo Static RAM.
200 MHz maximum clock rate
Data throughput up to 400 MBps
Bidirectional read write data strobe
Automotive AEC Q100 Grade 2 and 3
Optional DDR centre aligned read strobe
DDR transfers data on both edges of the clock
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