제조사부품번호

Alliance Memory SDRAM 1 GB Surface, 84-Pin 16 bit FBGA

RS 제품 번호:: 230-8437P
제조사 부품 번호:: AS4C64M16D2A-25BIN
제조업체:: Alliance Memory

Alliance Memory SDRAM 1 GB Surface, 84-Pin 16 bit FBGA

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대량 구매 할인 기용 가능

Subtotal 10 units (supplied in a tray)*

₩84,976.00

재고있음

2 개 단위 배송 준비 완료

더 자세한 내용이 필요하신가요? 필요한 수량을 입력하고 '배송일 확인'을 클릭하면 더 많은 재고 및 배송 세부정보를 확인하실 수 있습니다.

수량	한팩당
10 - 24	₩8,497.60
25 - 49	₩8,328.40
50 - 99	₩8,178.00
100 +	₩8,046.40

* 참고 가격: 실제 구매가격과 다를 수 있습니다

RS 제품 번호:: 230-8437P
제조사 부품 번호:: AS4C64M16D2A-25BIN
제조업체:: Alliance Memory

참조 문서

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제품 세부 사항

제품 정보를 선택해 유사 제품을 찾기

모두 선택	제품 정보	값
	브랜드	Alliance Memory
	Memory Size	1GB
	Product Type	SDRAM
	Organisation	64M x 16
	Data Bus Width	16bit
	Address Bus Width	13bit
	Maximum Clock Frequency	400MHz
	Number of Bits per Word	16
	Maximum Random Access Time	0.4ns
	Mount Type	Surface
	Package Type	FBGA
	Minimum Operating Temperature	-40°C
	Pin Count	84
	Maximum Operating Temperature	95°C
	Series	AS4C64M16D2A
	Height	1.2mm
	Width	12.5 mm
	Standards/Approvals	RoHS
	Length	8.1mm
	Automotive Standard	No
	Minimum Supply Voltage	1.7V
	Maximum Supply Voltage	1.9V

	모두 선택
	브랜드 Alliance Memory
	Memory Size 1GB
	Product Type SDRAM
	Organisation 64M x 16
	Data Bus Width 16bit
	Address Bus Width 13bit
	Maximum Clock Frequency 400MHz
	Number of Bits per Word 16
	Maximum Random Access Time 0.4ns
	Mount Type Surface
	Package Type FBGA
	Minimum Operating Temperature -40°C
	Pin Count 84
	Maximum Operating Temperature 95°C
	Series AS4C64M16D2A
	Height 1.2mm
	Width 12.5 mm
	Standards/Approvals RoHS
	Length 8.1mm
	Automotive Standard No
	Minimum Supply Voltage 1.7V
	Maximum Supply Voltage 1.9V

Datasheet - AS4C64M16D2A-25BIN

The Alliance Memory AS4C64M16D2A is a high-speed CMOS Double-Data-Rate-Two (DDR2), synchronous dynamic random- access memory (SDRAM) containing 1024 Mbits in a 16-bit wide data I/Os. It is internally configured as a 8-bank DRAM, 8 banks x 8Mb addresses x 16 I/Os. The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, Write latency = Read latency -1, Off-Chip Driver (OCD) impedance adjustment, and On Die Termination(ODT).

Supports JEDEC clock jitter specification

Fully synchronous operation

Fast clock rate: 400 MHz

Differential Clock, CK & CK#

Bidirectional single/differential data strobe DQS & DQS#

8 internal banks for concurrent operation

4-bit prefetch architecture