Intelligent Memory IM5116SDBBBG-6I SDRAM 512 MB Surface, 54-Pin 16 bit FBGA
- RS 제품 번호:
- 588-656
- 제조사 부품 번호:
- IM5116SDBBBG-6I
- 제조업체:
- Intelligent Memory
Subtotal (1 unit)*
₩22,992.40
재고있음
- 추가로 2026년 3월 16일 부터 10 개 단위 배송
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수량 | 한팩당 |
|---|---|
| 1 + | ₩22,992.40 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 588-656
- 제조사 부품 번호:
- IM5116SDBBBG-6I
- 제조업체:
- Intelligent Memory
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Intelligent Memory | |
| Memory Size | 512MB | |
| Product Type | SDRAM | |
| Organisation | 32M x 16 | |
| Data Bus Width | 16bit | |
| Address Bus Width | 13bit | |
| Number of Bits per Word | 16 | |
| Maximum Clock Frequency | 166MHz | |
| Maximum Random Access Time | 6ns | |
| Number of Words | 33554432 Words | |
| Mount Type | Surface | |
| Package Type | FBGA | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 54 | |
| Maximum Operating Temperature | 85°C | |
| Width | 8 mm | |
| Series | IM5116SDBB | |
| Height | 1.2mm | |
| Length | 8mm | |
| Standards/Approvals | RoHS | |
| Minimum Supply Voltage | 3V | |
| Supply Current | 140mA | |
| Maximum Supply Voltage | 3.6V | |
| Automotive Standard | AEC-Q100 | |
| 모두 선택 | ||
|---|---|---|
브랜드 Intelligent Memory | ||
Memory Size 512MB | ||
Product Type SDRAM | ||
Organisation 32M x 16 | ||
Data Bus Width 16bit | ||
Address Bus Width 13bit | ||
Number of Bits per Word 16 | ||
Maximum Clock Frequency 166MHz | ||
Maximum Random Access Time 6ns | ||
Number of Words 33554432 Words | ||
Mount Type Surface | ||
Package Type FBGA | ||
Minimum Operating Temperature -40°C | ||
Pin Count 54 | ||
Maximum Operating Temperature 85°C | ||
Width 8 mm | ||
Series IM5116SDBB | ||
Height 1.2mm | ||
Length 8mm | ||
Standards/Approvals RoHS | ||
Minimum Supply Voltage 3V | ||
Supply Current 140mA | ||
Maximum Supply Voltage 3.6V | ||
Automotive Standard AEC-Q100 | ||
The Intelligent Memory Four bank Synchronous DRAM is organized as 4 banks x 8Mbit x 16. It achieves high-speed data transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple bits and synchronizes the output data to the system clock. All control, address, data input, and output circuits are synchronized with the positive edge of an externally supplied clock to ensure precise timing and reliable performance.
Power down mode
Auto refresh and self refresh
Automatic and controlled precharge command
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