Intelligent Memory IM1G16D2DDBG-25 SDRAM 1 GB Surface, 84-Pin 16 bit FBGA-84 Ball
- RS 제품 번호:
- 588-592
- 제조사 부품 번호:
- IM1G16D2DDBG-25
- 제조업체:
- Intelligent Memory
Subtotal (1 pack of 2 units)*
₩14,024.80
재고있음
- 추가로 2026년 3월 16일 부터 50 개 단위 배송
더 자세한 내용이 필요하신가요? 필요한 수량을 입력하고 '배송일 확인'을 클릭하면 더 많은 재고 및 배송 세부정보를 확인하실 수 있습니다.
수량 | 한팩당 | 한팩당* |
|---|---|---|
| 2 + | ₩7,012.40 | ₩14,024.80 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 588-592
- 제조사 부품 번호:
- IM1G16D2DDBG-25
- 제조업체:
- Intelligent Memory
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Intelligent Memory | |
| Product Type | SDRAM | |
| Memory Size | 1GB | |
| Organisation | 64M x 16 | |
| Data Bus Width | 16bit | |
| Address Bus Width | 13bit | |
| Number of Bits per Word | 16 | |
| Maximum Clock Frequency | 533MHz | |
| Maximum Random Access Time | 2.5ns | |
| Number of Words | 67108864 Words | |
| Mount Type | Surface | |
| Package Type | FBGA-84 Ball | |
| Minimum Operating Temperature | -40°C | |
| Pin Count | 84 | |
| Maximum Operating Temperature | 95°C | |
| Height | 1.2mm | |
| Width | 8 mm | |
| Standards/Approvals | JEDEC, RoHS | |
| Length | 12.5mm | |
| Maximum Supply Voltage | 1.9V | |
| Automotive Standard | No | |
| Minimum Supply Voltage | 1.7V | |
| 모두 선택 | ||
|---|---|---|
브랜드 Intelligent Memory | ||
Product Type SDRAM | ||
Memory Size 1GB | ||
Organisation 64M x 16 | ||
Data Bus Width 16bit | ||
Address Bus Width 13bit | ||
Number of Bits per Word 16 | ||
Maximum Clock Frequency 533MHz | ||
Maximum Random Access Time 2.5ns | ||
Number of Words 67108864 Words | ||
Mount Type Surface | ||
Package Type FBGA-84 Ball | ||
Minimum Operating Temperature -40°C | ||
Pin Count 84 | ||
Maximum Operating Temperature 95°C | ||
Height 1.2mm | ||
Width 8 mm | ||
Standards/Approvals JEDEC, RoHS | ||
Length 12.5mm | ||
Maximum Supply Voltage 1.9V | ||
Automotive Standard No | ||
Minimum Supply Voltage 1.7V | ||
- COO (Country of Origin):
- TW
The Intelligent Memory Eight bank DDR DRAM is organized as 8 banks x 8Mbit x 16. It achieves high-speed data transfer rates by employing a chip architecture that prefetches multiple bits and synchronizes the output data to the system clock, ensuring efficient and reliable performance.
Power down mode
Auto refresh and self refresh
Automatic and controlled precharge command
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