Microchip ATSAMA5D27C-D1G-CU ARM Cortex A5 Microprocessor SAMA5D2 32 bit ARM 500 MHz 289-Pin LFBGA
- RS 제품 번호:
- 165-6445
- 제조사 부품 번호:
- ATSAMA5D27C-D1G-CU
- 제조업체:
- Microchip
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- RS 제품 번호:
- 165-6445
- 제조사 부품 번호:
- ATSAMA5D27C-D1G-CU
- 제조업체:
- Microchip
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Microchip | |
| Series | SAMA5D2 | |
| Product Type | Microprocessor | |
| Device Core | ARM Cortex A5 | |
| Data Bus Width | 32bit | |
| Instruction Set Architecture | ARM | |
| Maximum Clock Frequency | 500MHz | |
| Mount Type | Surface | |
| Package Type | LFBGA | |
| Minimum Supply Voltage | 1.2V | |
| Maximum Supply Voltage | 3.6V | |
| Pin Count | 289 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Length | 14mm | |
| Height | 1.2mm | |
| Width | 14 mm | |
| Standards/Approvals | RoHS | |
| Number of Cores | 1 | |
| Automotive Standard | No | |
| 모두 선택 | ||
|---|---|---|
브랜드 Microchip | ||
Series SAMA5D2 | ||
Product Type Microprocessor | ||
Device Core ARM Cortex A5 | ||
Data Bus Width 32bit | ||
Instruction Set Architecture ARM | ||
Maximum Clock Frequency 500MHz | ||
Mount Type Surface | ||
Package Type LFBGA | ||
Minimum Supply Voltage 1.2V | ||
Maximum Supply Voltage 3.6V | ||
Pin Count 289 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Length 14mm | ||
Height 1.2mm | ||
Width 14 mm | ||
Standards/Approvals RoHS | ||
Number of Cores 1 | ||
Automotive Standard No | ||
The SAMA5D27C-D1G System in Package (SiP) integrates the ARM® Cortex®-A5 processor-based SAMA5D27C MPU with 1 Gbit (128 Mbytes) of DDR2-SDRAM in a single package. By combining the high-performance, ultra-low-power SAMA5D2 with DDR2-SDRAM in a single package, PCB routing complexity, area and number of layers is reduced in the majority of cases. This makes board design easier and more robust by facilitating design for EMI, ESD and signal integrity. This SiP targets applications using Linux OS and is available in a BGA289 package.
ARM Cortex-A5 core
Memory Architecture
Memory Management Unit
32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache
128-Kbyte L2 cache configurable to be used as an internal SRAM
1Gb DDR2-SDRAM
One 128-Kbyte scrambled internal SRAM
8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC)
Low-Power Modes
Ultra Low-power mode with fast wakeup capability
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