Microchip AT91SAM9N12-CUR ARM926EJ-S Microprocessor SAM9N12 32 bit ARM 400 MHz 217-Pin BGA
- RS 제품 번호:
- 775-389
- 제조사 부품 번호:
- AT91SAM9N12-CUR
- 제조업체:
- Microchip
N
Subtotal (1 reel of 500 units)*
₩6,876,675.00
일시적 품절
- 2026년 7월 02일 부터 배송
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수량 | 한팩당 | 릴당* |
|---|---|---|
| 500 + | ₩13,753.35 | ₩6,877,065.00 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 775-389
- 제조사 부품 번호:
- AT91SAM9N12-CUR
- 제조업체:
- Microchip
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모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Microchip | |
| Product Type | Microprocessor | |
| Series | SAM9N12 | |
| Device Core | ARM926EJ-S | |
| Data Bus Width | 32bit | |
| Instruction Set Architecture | ARM | |
| Maximum Clock Frequency | 400MHz | |
| Interface Type | ADC, LCD, SPI, USART, USB | |
| Mount Type | Surface Mount | |
| Minimum Supply Voltage | 0.9V | |
| Package Type | BGA | |
| Pin Count | 217 | |
| Maximum Supply Voltage | 1.1V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Width | 15mm | |
| Height | 1.4mm | |
| Length | 14mm | |
| Number of Cores | 1 | |
| Automotive Standard | No | |
| 모두 선택 | ||
|---|---|---|
브랜드 Microchip | ||
Product Type Microprocessor | ||
Series SAM9N12 | ||
Device Core ARM926EJ-S | ||
Data Bus Width 32bit | ||
Instruction Set Architecture ARM | ||
Maximum Clock Frequency 400MHz | ||
Interface Type ADC, LCD, SPI, USART, USB | ||
Mount Type Surface Mount | ||
Minimum Supply Voltage 0.9V | ||
Package Type BGA | ||
Pin Count 217 | ||
Maximum Supply Voltage 1.1V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Width 15mm | ||
Height 1.4mm | ||
Length 14mm | ||
Number of Cores 1 | ||
Automotive Standard No | ||
- COO (Country of Origin):
- CN
The Microchip microprocessor serves as a powerful foundation for multi-tasking applications, optimising performance and power efficiency with its Advanced architecture and integrated features.
Supports both 32-bit ARM and 16-bit Thumb instruction sets for flexible performance
Features a Memory Management Unit (MMU) for comprehensive memory control
Incorporates Harvard architecture with separate instruction and data buses for enhanced throughput
Offers tightly-coupled memory interfaces for reduced latency in critical applications