Microchip AT91SAM9G25-BFU-999 ARM926EJ-S Microprocessor SAM9G25 32 bit ARM 400 MHz 247-Pin VFBGA
- RS 제품 번호:
- 775-376
- 제조사 부품 번호:
- AT91SAM9G25-BFU-999
- 제조업체:
- Microchip
N
Subtotal (1 reel of 1000 units)*
₩15,003,300.00
현재 액세스할 수 없는 재고 정보 - 나중에 다시 확인해 주세요.
수량 | 한팩당 | 릴당* |
|---|---|---|
| 1000 + | ₩15,003.30 | ₩15,002,520.00 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 775-376
- 제조사 부품 번호:
- AT91SAM9G25-BFU-999
- 제조업체:
- Microchip
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모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Microchip | |
| Product Type | Microprocessor | |
| Series | SAM9G25 | |
| Device Core | ARM926EJ-S | |
| Data Bus Width | 32bit | |
| Instruction Set Architecture | ARM | |
| Maximum Clock Frequency | 400MHz | |
| Interface Type | ADC, LCD, SPI, USART, USB | |
| Mount Type | Surface Mount | |
| Package Type | VFBGA | |
| Minimum Supply Voltage | 0.9V | |
| Maximum Supply Voltage | 1.1V | |
| Pin Count | 247 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Automotive Standard | No | |
| Number of Cores | 1 | |
| 모두 선택 | ||
|---|---|---|
브랜드 Microchip | ||
Product Type Microprocessor | ||
Series SAM9G25 | ||
Device Core ARM926EJ-S | ||
Data Bus Width 32bit | ||
Instruction Set Architecture ARM | ||
Maximum Clock Frequency 400MHz | ||
Interface Type ADC, LCD, SPI, USART, USB | ||
Mount Type Surface Mount | ||
Package Type VFBGA | ||
Minimum Supply Voltage 0.9V | ||
Maximum Supply Voltage 1.1V | ||
Pin Count 247 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Automotive Standard No | ||
Number of Cores 1 | ||
- COO (Country of Origin):
- TW
The Microchip versatile microprocessor is designed primarily for multi-tasking applications, featuring robust memory management capabilities alongside high performance. Its efficient execution supports both ARM and Thumb instruction sets, enhancing code density.
Supports both 32-bit ARM and 16-bit Thumb instruction sets for flexible coding
Includes a Memory Management Unit (MMU) for improved task handling and system management
Features separate instruction and data caches, optimising performance across operations
Provides tightly-coupled memory interfaces for minimal latency and enhanced speed
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