Nexperia 74HC73D-Q100J Flip Flop IC HC, CMOS, 14-Pin SO-14
- RS 제품 번호:
- 243-4416
- 제조사 부품 번호:
- 74HC73D-Q100J
- 제조업체:
- Nexperia
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대량 구매 할인 기용 가능
Subtotal (1 pack of 25 units)*
₩15,112.50
재고있음
- 추가로 2026년 4월 27일 부터 1,900 개 단위 배송
더 자세한 내용이 필요하신가요? 필요한 수량을 입력하고 '배송일 확인'을 클릭하면 더 많은 재고 및 배송 세부정보를 확인하실 수 있습니다.
수량 | 한팩당 | 한팩당* |
|---|---|---|
| 25 - 25 | ₩604.50 | ₩15,132.00 |
| 50 - 75 | ₩590.85 | ₩14,781.00 |
| 100 - 225 | ₩577.20 | ₩14,410.50 |
| 250 - 975 | ₩563.55 | ₩14,079.00 |
| 1000 + | ₩547.95 | ₩13,708.50 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 243-4416
- 제조사 부품 번호:
- 74HC73D-Q100J
- 제조업체:
- Nexperia
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Nexperia | |
| Logic Family | HC | |
| Product Type | Flip Flop IC | |
| Input Type | Single Ended | |
| Output Type | CMOS | |
| Polarity | Negative | |
| Mount Type | Surface | |
| Minimum Supply Voltage | 2V | |
| Package Type | SO-14 | |
| Pin Count | 14 | |
| Maximum Supply Voltage | 6V | |
| Trigger Type | Negative Edge | |
| Minimum Operating Temperature | -40°C | |
| Flip-Flop Type | JK Type | |
| Maximum Operating Temperature | 125°C | |
| Standards/Approvals | HBM JESD22-A114F, AEC-Q100 (Grade 1), JEDEC Standards JESD8C (2.7 V to 3.6 V), JESD7A (2.0 V to 6.0 V), MM JESD22-A115-A | |
| Series | 74HC73-Q100 | |
| Automotive Standard | AEC-Q100 Grade 1 | |
| 모두 선택 | ||
|---|---|---|
브랜드 Nexperia | ||
Logic Family HC | ||
Product Type Flip Flop IC | ||
Input Type Single Ended | ||
Output Type CMOS | ||
Polarity Negative | ||
Mount Type Surface | ||
Minimum Supply Voltage 2V | ||
Package Type SO-14 | ||
Pin Count 14 | ||
Maximum Supply Voltage 6V | ||
Trigger Type Negative Edge | ||
Minimum Operating Temperature -40°C | ||
Flip-Flop Type JK Type | ||
Maximum Operating Temperature 125°C | ||
Standards/Approvals HBM JESD22-A114F, AEC-Q100 (Grade 1), JEDEC Standards JESD8C (2.7 V to 3.6 V), JESD7A (2.0 V to 6.0 V), MM JESD22-A115-A | ||
Series 74HC73-Q100 | ||
Automotive Standard AEC-Q100 Grade 1 | ||
The Nexperia dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output high. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
CMOS low-power dissipation
Wide supply voltage range from 2.0 to 6.0 V
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
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