Renesas Electronics 2305-1HDCG Clock Buffer 8-Pin SOIC
- RS 제품 번호:
- 263-7866
- 제조사 부품 번호:
- 2305-1HDCG
- 제조업체:
- Renesas Electronics
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대량 구매 할인 기용 가능
Subtotal (1 tube of 97 units)*
₩83,338.52
재고있음
- 1,261 개 단위 배송 준비 완료
더 자세한 내용이 필요하신가요? 필요한 수량을 입력하고 '배송일 확인'을 클릭하면 더 많은 재고 및 배송 세부정보를 확인하실 수 있습니다.
수량 | 한팩당 | Per Tube* |
|---|---|---|
| 97 - 194 | ₩859.16 | ₩83,374.24 |
| 291 - 485 | ₩834.72 | ₩80,877.60 |
| 582 - 970 | ₩817.80 | ₩79,253.28 |
| 1067 + | ₩793.36 | ₩76,865.68 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 263-7866
- 제조사 부품 번호:
- 2305-1HDCG
- 제조업체:
- Renesas Electronics
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 133MHz | |
| Mount Type | Surface | |
| Maximum Propagation Delay Time | 350ps | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Number of Outputs | 5 | |
| Minimum Supply Voltage | 3V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Height | 1.75mm | |
| Length | 5mm | |
| Series | IDT2305 | |
| Standards/Approvals | RoHS | |
| Width | 4 mm | |
| Automotive Standard | No | |
| 모두 선택 | ||
|---|---|---|
브랜드 Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 133MHz | ||
Mount Type Surface | ||
Maximum Propagation Delay Time 350ps | ||
Package Type SOIC | ||
Pin Count 8 | ||
Number of Outputs 5 | ||
Minimum Supply Voltage 3V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Height 1.75mm | ||
Length 5mm | ||
Series IDT2305 | ||
Standards/Approvals RoHS | ||
Width 4 mm | ||
Automotive Standard No | ||
The Renesas Electronics high-speed phase-lock loop clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. It is an 8-pin version of the accepts one reference input, and drives out five low skew clocks.
Phase lock loop clock distribution
Distributes one clock input to one bank of five outputs
No external RC network required
Power down mode
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