Microchip, 8bit 8 bit MCU, PIC18F46Q84 Microcontroller, 64MHz, 64 kb Flash, 44-Pin TQFP
- RS 제품 번호:
- 631-518
- 제조사 부품 번호:
- PIC18F46Q84-E/PTVAO
- 제조업체:
- Microchip
N
Subtotal (1 Box of 480 units)*
₩1,799,385.60
일시적 품절
- 2026년 1월 15일 부터 배송
더 자세한 내용이 필요하신가요? 필요한 수량을 입력하고 '배송일 확인'을 클릭하면 더 많은 재고 및 배송 세부정보를 확인하실 수 있습니다.
수량 | 한팩당 | Per Box* |
|---|---|---|
| 480 + | ₩3,748.72 | ₩1,799,656.32 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 631-518
- 제조사 부품 번호:
- PIC18F46Q84-E/PTVAO
- 제조업체:
- Microchip
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Microchip | |
| Family Name | PIC18F46Q84 | |
| Package Type | TQFP | |
| Mounting Type | Surface Mount | |
| Pin Count | 44 | |
| Device Core | 8 bit MCU | |
| Data Bus Width | 8bit | |
| Program Memory Size | 64 kb | |
| Maximum Frequency | 64MHz | |
| Program Memory Type | Flash | |
| 모두 선택 | ||
|---|---|---|
브랜드 Microchip | ||
Family Name PIC18F46Q84 | ||
Package Type TQFP | ||
Mounting Type Surface Mount | ||
Pin Count 44 | ||
Device Core 8 bit MCU | ||
Data Bus Width 8bit | ||
Program Memory Size 64 kb | ||
Maximum Frequency 64MHz | ||
Program Memory Type Flash | ||
- COO (Country of Origin):
- TH
The Microchip 8 bit MCUs expands by combining an extensive array of Core Independent Peripherals (CIPs) with Controller Area Network Flexible Data Rate (CAN FD). These cost optimized MCUs contain time-saving CIPs in up to 48-pins with up to 128 KB of flash memory. The family introduces new features and peripherals like the Universal Timer (UTMR) with customization capability
context switching added to the 12-bit ADC with Computation for automating analogue signal analysis for real-time system response.
Data transfers capabilities
User programmable source and destination sizes
Hardware and software triggered data transfers
Fixed interrupt latency of three instruction cycles
Programmable vector table base address
Backwards compatible with previous interrupt capabilities
User programmable source and destination sizes
Hardware and software triggered data transfers
Fixed interrupt latency of three instruction cycles
Programmable vector table base address
Backwards compatible with previous interrupt capabilities
관련된 링크들
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