Renesas Electronics 9DBV0431AKILF Buffer 32-Pin QFN
- RS 제품 번호:
- 249-4404
- 제조사 부품 번호:
- 9DBV0431AKILF
- 제조업체:
- Renesas Electronics
Subtotal (1 tray of 490 units)*
₩1,940,968.40
일시적 품절
- 2026년 3월 30일 부터 배송
더 자세한 내용이 필요하신가요? 필요한 수량을 입력하고 '배송일 확인'을 클릭하면 더 많은 재고 및 배송 세부정보를 확인하실 수 있습니다.
수량 | 한팩당 | Per Tray* |
|---|---|---|
| 490 + | ₩3,961.16 | ₩1,940,784.16 |
* 참고 가격: 실제 구매가격과 다를 수 있습니다
- RS 제품 번호:
- 249-4404
- 제조사 부품 번호:
- 9DBV0431AKILF
- 제조업체:
- Renesas Electronics
사양
참조 문서
제정법과 컴플라이언스
제품 세부 사항
제품 정보를 선택해 유사 제품을 찾기
모두 선택 | 제품 정보 | 값 |
|---|---|---|
| 브랜드 | Renesas Electronics | |
| Number of Elements per Chip | 4 | |
| Maximum Supply Current | 4 mA | |
| Maximum Input Frequency | 137.5MHz | |
| Mounting Type | Surface Mount | |
| Package Type | QFN | |
| Pin Count | 32 | |
| 모두 선택 | ||
|---|---|---|
브랜드 Renesas Electronics | ||
Number of Elements per Chip 4 | ||
Maximum Supply Current 4 mA | ||
Maximum Input Frequency 137.5MHz | ||
Mounting Type Surface Mount | ||
Package Type QFN | ||
Pin Count 32 | ||
The Renesas Electronics 9DBV0431 is a 4-output very low power buffer for 100 MHz PCIe Gen1, Gen2 and Gen3 applications. It can also be used for 50M or 125M Ethernet Applications via software frequency selection. The device has 4 output enables for clock management.
1.8 V operation: minimal power consumption
OE# pins: support DIF power management
HCSL compatible differential input: can be driven by common clock sources
LP-HCSL differential clock outputs: reduced power and board space
Programmable slew rate for each output: allows tuning for various line lengths
Programmable output amplitude: allows tuning for various application environments
Pin/software selectable PLL bandwidth and PLL Bypass: minimize phase jitter for each application
Outputs blocked until PLL is locked: clean system start-up
Software selectable 50 MHz or 125 MHz PLL operation: useful for Ethernet applications
Configuration can be accomplished with strapping pins: SMBus interface not required for device control
3.3 V tolerant SMBus interface works with legacy controllers
OE# pins: support DIF power management
HCSL compatible differential input: can be driven by common clock sources
LP-HCSL differential clock outputs: reduced power and board space
Programmable slew rate for each output: allows tuning for various line lengths
Programmable output amplitude: allows tuning for various application environments
Pin/software selectable PLL bandwidth and PLL Bypass: minimize phase jitter for each application
Outputs blocked until PLL is locked: clean system start-up
Software selectable 50 MHz or 125 MHz PLL operation: useful for Ethernet applications
Configuration can be accomplished with strapping pins: SMBus interface not required for device control
3.3 V tolerant SMBus interface works with legacy controllers
For these non-cancellable (NC), and non-returnable (NR) products, Terms and Conditions apply.
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